The present invention relates to integrated semiconductor component fabrication and, more particularly, to process etch control for multiple semiconductor devices comprising dissimilar material configurations on a common substrate.
Semiconductor components, such as those associated with electronic and optoelectronic applications, frequently comprise layered heterostructures of semiconductor materials. The semiconductor devices that form the components are commonly fabricated in a layer upon layer process in the vertical direction upon a common layer or substrate. The layers are selectively deposited and portions removed defining semiconductor devices using deposition and material removing processes. These layers can be on the order of nanometers in thickness. The methods are used to create devices, such as diodes and transistors.
An integrated semiconductor component may consist of a plurality of semiconductor devices of various material compositions and thickness interconnected on a common layer or substrate. Integrated semiconductor components have been enabling multi-function capability, such as, but not limited to, laser, modulator, and detector devices, to be integrated onto a common substrate. Integrated semiconductor fabrication processes can be very complex. For example, planar monolithic integration commonly requires that a plurality of epitaxial (epi)xe2x80x94deposited devices of dissimilar composition and dimension extend from a common planar layer, such as a bottom n+ contact layer.
However, devices are formed from device layers having dissimilar composition and dimension, and therefore different overall etch rates. These different etch rates preclude the use of one etch process to simultaneously etch all unnecessary portions of the device layer to the common layer. Because of these differential etch rates, complex processing, such as sequential etch for each device type, is employed. Such processing is costly and low yielding.
FIGS. 20A, 20B, and 20C are cross-sectional views of an example of a result of using one etch process to form multiple dissimilar devices. FIG. 20A is a cross-sectional view of a first device layer 19 and an adjacent second device layer 29 extending from a common layer 9, prior to etching. The elevation of a first device surface 51 is substantially coplanar with that of a second device surface 52, to ultimately produce two devices having substantially co-planar surfaces required for a particular purpose. The co-planar relationship between the devices may not be required in other embodiments, and is not limited thereto. First and second etch masks 39a,39b are formed upon the first and second device layer surfaces 51,52, respectively, defining exposed portions 93 that are to be removed from the common layer 9 by the etch process. The first device layer 19 has a higher etch rate than the second device layer 29.
FIG. 20B is a cross-sectional view of the result during the selected etch process. The exposed portion 93 of the first device layer 19 has been substantially removed from the common layer 9. The exposed portion of the second device layer 29 is in the process of being removed forming a partially etched second device layer 59.
FIG. 20C is a cross-sectional view of the result at the completion of the etch process, wherein substantially all of the exposed partially etched second device layer 59 has been removed from the common layer 9. The exposed common layer 9 adjacent the first device 49 is now etched through to an under-layer 91 as well. The discontinuity of the common layer 9 between the first device 49 and second device 79 results in a defective product.
In the course of fabrication, some processing steps leave an exposed device side wall 39a,39b. These side walls form conductive oxide layers in some material configurations, such as, but not limited to, InP- and InGaAsP-containing configurations. The side wall 39a,39b is, therefore, subsequently passivated so that no leakage current will exist between individual material layers forming the device 49,79, and/or between the layer above to the layer below 91 the device. Commonly, passivation is achieved by the application of an encasing passivation layer, such as, but not limited to, BCB polymer and PMMA photoresist, that is spun around and over the device to encapsulate the side wall 39a,39b. 
Another issue in the fabrication of integrated semiconductor components is providing interlayer interconnection. One approach in larger-scale component fabrication is the use of vias; a cylindrical bore-like feature extending through a dielectric layer from one layer to another, that can be provided with electrically conductive material to effect an interconnection with devices on various layers. Vias for larger-scale components are commonly formed using mechanical drilling. Etch processing of the vias for nanometer-scale devices is problematic, including, but not limited to, adding additional steps to the fabrication process and being sensitive to etch solution variations.
New methods are needed for the fabrication of integrated semiconductor components that provide etch speed modification to effectively etch multiple dissimilar materials to a common layer or substrate with a common etch process, self-aligned via formation, and/or planarization-between two or more devices. The methods would preferably provide a process that is less complex, more forgiving, have a low defect rate, impart little to no harm to the underlying desired material layers, and/or are reasonably economical.